High speed, high current bus driver circuits for an output buffer are utilized to rapidly charge or discharge a data bus to a high or low voltage level. Typically, when this rapid charging and discharging occurs the resulting effect can often be a damped oscillation or ringing of current flowing through the buffer. This ringing effect is undersirable because it can cause false information or false data to be provided to the bus.
The network formed by the output buffer, its interconnects and the load on the data bus can be represented by an RLC equivalent circuit. In this type of equivalent circuit, the inductance, L, is due to the inherent parasitic self inductance of the leads connected to the buffer circuit, the capacitance C is due to the capacitive load of the devices connected to the bus, and the resistance R is the resistance of the charging or discharging path.
The resistance R acts as a dissipating element in order that the oscillation of the circuit decays. The ratio of the resistance R and the critical resistance factor 2(L/C).sup.1/2 determines the amount of damping the circuit will experience while dissipating its power.
This damped ringing can cause unintentional triggering of the devices connected to the data bus if the voltage amplitude of an oscillation cycle exceeds the logical threshold of the device. Since this damped oscillation will also be present on the power supply lines of the bus driver circuit, other circuits such as an input buffer circuit sharing the same power line will likely experience voltage failures due to the distortion of the power supply voltage. Finally, a noisy power supply is likely to cause ringing on the data which has been driven to that power rail by other bus drivers sharing the power line. This ringing is likely to happen regardless of the amount of self inductance L that the other bus drivers have on their leads.
The voltage amplitude of this damped ringing is a function of the rate change of the current (di/dt). Since the values of the parasitic physical elements L and C of the driver network are constant, their effect on the current cannot be altered. However, one possible way of controlling the rate of change of current would be to control the flow of current through the driver transistors that form a portion of the output buffer circuit.
With this solution there is a trade off between propagation delay which slows the bus driver circuit down and the clamping voltage or the amplitude of the signals that are provided to the gates of the driver transistors. A circuit addressing this problem is described in U.S. Pat. No. 4,877,980, entitled, "Time Variant Drive Circuit For High Speed Bus Driver To Limit Oscillation Or Ringing On A Bus," and assigned to the assignee of this patent application. In this patent a bias voltage (V.sub.bias) is applied to one of gate of a p channel and n channel transistor pair. In this patent the bias voltage is chosen to prevent ringing on the bus. Although the invention described in this patent works satisfactorily for its intended purposes, it does not disclose a means for providing the V.sub.bias voltage. The driver circuit disclosed in this patent does not show as implementation that will minimize oscillation while minimizing the power. For the low voltage situations the minimizing of power is a critical feature.
Accordingly, what is needed is a circuit for providing a voltage to the driver transistors of a driver circuit that is flexible and is simple to implement. What is also needed, is a an output buffer circuit which minimizes the damped ringing or oscillation problem associated with previously known output buffer circuits at the same time it is not appreciably effected by the propagation delays that can be generated when regulating the rate of change of the current. Finally, what is needed is an output buffer circuit which will use a limited amount of power in operation.
The present invention provides a output buffer circuit which controls the amplitude and slew rate of the gate voltages of the driver transistors while providing better immunity to power supply changes and process variations that are inherent in the semiconductor device. The output buffer circuit also includes means for limiting the power dissipated while maximizing its current sinking and sourcing capability.